1. Field of the Invention
This invention relates to the field of phase-lock loops, and in particular to a phase/frequency detector having a reduced blind spot.
2. Description of the Related Art
FIG. 1 shows a classic phase-lock loop (PLL) 100 configured to operate as a frequency multiplier. This is an illustrative application of a PLL which is chosen from a wide variety of well known applications. Three components that are present in every PLL are the phase detector 102, the charge pump and/or filter 104, and the voltage controlled oscillator 106. The phase detector 102 measures the phase difference between incoming clock signals and produces a phase error signal indicative of whether the reference signal should be shifted upward or downward in phase. The error signal produced by the phase detector 102 is processed by the charge pump and/or filter 104 to produce a control voltage. The voltage controlled oscillator 106 provides an output clock signal with a frequency that is controlled by the control voltage. As the control voltage increases or decreases, the output clock frequency increases or decreases correspondingly. In the frequency multiplier configuration shown in FIG. 1, the output clock signal is fed back to the phase detector through a frequency divider 108. The frequency divider 108 produces a reference frequency which is a fraction of the output clock frequency. Hence, when the reference frequency is "locked" to the input clock frequency, the output clock frequency is a multiple of the input clock frequency.
Microprocessor frequencies are getting higher every year. PLL designs must be constantly improved to keep up. Most of the PLL design effort is spent in the voltage-controlled oscillator and charge pump design. The other critical component, the phase detector has not seen significant improvement, and has remained almost unchanged. Yet many parameters of PLLs, including tracking range, acquisition range, loop gain, and transient response, depend on the properties of the phase detectors employed.
Existing phase detector designs are characterized by the following properties: (1) the input-phase difference range for which the error signal is monotonic, (2) the response to unequal input frequencies, and (3) the response to varying input signal amplitudes and duty cycles.
The well-known Gilbert cell is an analog signal multiplier, which for sinusoidal signals, produces a DC value proportional to the cosine of the phase difference for small phase differences. The response of the Gilbert cell is highly sensitive to the amplitude and duty cycle of the input frequencies, which is generally undesirable. The amplitude sensitivity may be eliminated by increasing the gain of the multiplier so that the output signal saturates, and the Gilbert cell acts like an XOR gate. The average DC value of the XOR gate has the phase-difference response shown in FIG. 2. The range for which the DC output is monotonic is for phase errors between 0 and .pi. (180.degree.).
An R-S flip flop such as that shown in FIG. 5 may also be used as a phase detector. Although a NOR implementation is shown, NAND implementations are also popular. The R-S flip flop is configured so that a rising edge of the input clock signal latches the output high. The rising edge of the reference clock signal then resets the latch, return the output to low. The average DC response of this phase detector is insensitive to variations of the clock duty cycle of the input signal, and is shown in FIG. 3. The phase error range for which the DC output is monotonic is between 0 and 2 .pi. (360.degree.).
The type of detector most commonly used in PLLs is a phase-frequency detector (PFD). A PFD has two non-complementary outputs. The first output (the UP signal) is driven high if a rising edge of the input clock precedes a rising edge of the reference clock. The second output (the DowN signal) is driven high if a rising edge of the reference clock precedes a rising edge of the input clock. In both cases, the second rising edge resets both outputs low. A state diagram illustrating this behavior is shown in FIG. 6. The resulting response of the PFD is shown in FIG. 4. The range for which the DC output is monotonic is between -2 .pi. to +2 .pi.. FIG. 7 shows an R-S flip flop implementation of the PFD.
It is noted that the detector responses shown in FIGS. 2, 3 and 4 represent ideal responses, and that the actual responses of implemented phase detectors depart from the ideal. PFDs suffer from two non-ideal characteristics termed: the "dead zone" and the "blind spot". The dead zone is a region near zero phase error (.DELTA..phi.=0) in which the edges of the input and reference signals are so close together that the UP and DN outputs are not provided with sufficient opportunity to fully switch and thereby drive the charge pump. As a result, the response to a small phase error is less than it should be, i.e. the response is "deadened". This problem has been dealt with in the past by reducing the propagation time from detector input to output (to make the dead zone smaller) and by allowing both the UP and DN outputs to go high at the same time during the reset (to reduce the deadening effect).
The blind spot is the region near .+-.2 .pi. in which the leading edge of a subsequent cycle is arriving during the reset of the PFD, i.e. while the PFD is "blind". The effect of the blind spot is to decrease the range in which the PFD is monotonic, thereby reducing tracking range and pull-in range, and increasing lock acquisition time. It is desirable to provide a PFD with a response that closely approximates the ideal phase error response.